1/*
2 * Copyright (c) 2007-2023 Apple Inc. All rights reserved.
3 * Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved.
4 */
5#ifndef _PEXPERT_ARM_BOARD_CONFIG_H
6#define _PEXPERT_ARM_BOARD_CONFIG_H
7
8#include <mach/machine.h>
9
10/*
11 * Per-SoC configuration. General order is:
12 *
13 * CPU type
14 * CPU configuration
15 * CPU feature disables / workarounds
16 * CPU topology
17 * Other platform configuration (e.g. DARTs, PPL)
18 *
19 * This should answer the question: "what's unique about this SoC?"
20 *
21 * arm64/H*.h should answer the question: "what's unique about this CPU core?"
22 *
23 * For __ARM_AMP__ systems that have different cache line sizes on different
24 * clusters, MAX_L2_CLINE must reflect the largest L2 cache line size
25 * across all clusters.
26 */
27
28#ifdef ARM64_BOARD_CONFIG_T6000
29#include <pexpert/arm64/H13.h>
30
31
32#define MAX_L2_CLINE 7
33#define MAX_CPUS 10
34#define MAX_CPU_CLUSTERS 3
35#define MAX_CPU_CLUSTER_PHY_ID 10
36#define HAS_IOA 1
37
38#define PMAP_CS 1
39#define PMAP_CS_ENABLE 1
40#define XNU_MONITOR 1 /* Secure pmap runtime */
41#define __ARM_42BIT_PA_SPACE__ 1
42#define USE_APPLEARMSMP 1
43#if DEVELOPMENT || DEBUG
44#define XNU_ENABLE_PROCESSOR_EXIT 1 /* Enable xnu processor_exit() by default */
45#endif
46#define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */
47#endif /* ARM64_BOARD_CONFIG_T6000 */
48
49#ifdef ARM64_BOARD_CONFIG_T6020
50#include <pexpert/arm64/H14.h>
51
52#define MAX_L2_CLINE 7
53#define MAX_CPUS 24
54#define MAX_CPU_CLUSTERS 6
55#define MAX_CPU_CLUSTER_PHY_ID 10
56#define HAS_IOA 1
57
58#define PMAP_CS 1
59#define PMAP_CS_ENABLE 1
60#define XNU_MONITOR 1 /* Secure pmap runtime */
61#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
62#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
63#define XNU_MONITOR_UAT_PPL 1 /* UAT PPL plugin for secure pmap runtime */
64#if HIBERNATION
65#define XNU_MONITOR_PPL_HIB 1 /* HMAC SHA driver exposed as a PPL plugin */
66#endif /* HIBERNATION */
67#define XNU_MONITOR_T6000_DART 1
68#define XNU_MONITOR_T8110_DART 1 /* T8110 DART plugin for secure pmap runtime */
69#define __ARM_42BIT_PA_SPACE__ 1
70#define USE_APPLEARMSMP 1
71#define XNU_CLUSTER_POWER_DOWN 1 /* Enable xnu cluster power down by default */
72#define RHODES_CLUSTER_POWERDOWN_WORKAROUND 1 /* Workaround for rdar://89107373 (Rhodes cluster power down: cannot manually power down and up a core multiple times without powering down the cluster) */
73#define XNU_PLATFORM_ERROR_HANDLER 1 /* This platform uses the platform error handler inside XNU rather than a kext */
74#define XNU_HANDLE_ECC 1 /* This platform may support ECC error recovery */
75#define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */
76#endif /* ARM64_BOARD_CONFIG_T6020 */
77
78
79
80
81
82
83
84
85#ifdef ARM64_BOARD_CONFIG_T8101
86#include <pexpert/arm64/H13.h>
87
88#define MAX_L2_CLINE 7
89#define MAX_CPUS 8
90#define MAX_CPU_CLUSTERS 2
91
92#define PMAP_CS 1
93#define PMAP_CS_ENABLE 1
94#define XNU_MONITOR 1 /* Secure pmap runtime */
95#endif /* ARM64_BOARD_CONFIG_T8101 */
96
97#ifdef ARM64_BOARD_CONFIG_T8103
98#include <pexpert/arm64/H13.h>
99
100#define MAX_L2_CLINE 7
101#define MAX_CPUS 8
102#define MAX_CPU_CLUSTERS 2
103
104#define PMAP_CS 1
105#define PMAP_CS_ENABLE 1
106#define XNU_MONITOR 1 /* Secure pmap runtime */
107#endif /* ARM64_BOARD_CONFIG_T8103 */
108
109
110#ifdef ARM64_BOARD_CONFIG_T8112
111#include <pexpert/arm64/H14.h>
112
113#define MAX_L2_CLINE 7
114#define MAX_CPUS 8 /* Actually has 6 CPUs, see doc/xnu_build_consolidation.md for more info */
115#define MAX_CPU_CLUSTERS 2
116
117#define PMAP_CS 1
118#define PMAP_CS_ENABLE 1
119#define XNU_MONITOR 1 /* Secure pmap runtime */
120#define USE_APPLEARMSMP 1
121#endif /* ARM64_BOARD_CONFIG_T8112 */
122
123
124
125
126
127
128
129
130
131
132
133#ifdef ARM64_BOARD_CONFIG_BCM2837
134#include <pexpert/arm64/BCM2837.h>
135
136#define MAX_L2_CLINE 6
137#define MAX_CPUS 4
138#define MAX_CPU_CLUSTERS 1
139
140#define CORE_NCTRS 8 /* Placeholder; KPC is not enabled for this target */
141#endif /* ARM64_BOARD_CONFIG_BCM2837 */
142
143#ifdef ARM64_BOARD_CONFIG_VMAPPLE
144#include <pexpert/arm64/VMAPPLE.h>
145
146#define MAX_L2_CLINE 7
147#define MAX_CPUS 32 /* limited by CPU copy window size and cpu checkin mask */
148#define MAX_CPU_CLUSTERS 1
149
150#define CORE_NCTRS 2
151
152#define USE_APPLEARMSMP 1
153
154#if XNU_TARGET_OS_WATCH
155#define PREFER_ARM64_32_BINARIES 1
156#endif
157
158#endif /* ARM64_BOARD_CONFIG_VMAPPLE */
159
160
161#ifndef HAS_UNCORE_CTRS
162#undef UNCORE_VERSION
163#undef UNCORE_PER_CLUSTER
164#undef UNCORE_NCTRS
165#endif
166
167#if MAX_CPU_CLUSTERS == 1
168#undef __ARM_AMP__
169#endif
170
171#ifndef MAX_CPU_CLUSTER_PHY_ID
172#define MAX_CPU_CLUSTER_PHY_ID (MAX_CPU_CLUSTERS - 1)
173#endif
174
175#ifdef PREFER_ARM64_32_BINARIES
176#define PREFERRED_USER_CPU_TYPE CPU_TYPE_ARM64_32
177#define PREFERRED_USER_CPU_SUBTYPE CPU_SUBTYPE_ARM64_32_V8
178#endif
179
180
181/*
182 * Some platforms have very expensive timebase routines. An optimization
183 * is to avoid switching timers on kernel exit/entry, which results in all
184 * time billed to the system timer. However, when exposed to userspace, it's
185 * reported as user time to indicate that work was done on behalf of
186 * userspace.
187 */
188
189#if CONFIG_SKIP_PRECISE_USER_KERNEL_TIME
190#define PRECISE_USER_KERNEL_TIME HAS_FAST_CNTVCT
191#else /* CONFIG_SKIP_PRECISE_USER_KERNEL_TIME */
192#define PRECISE_USER_KERNEL_TIME 1
193#endif /* !CONFIG_SKIP_PRECISE_USER_KERNEL_TIME */
194
195/**
196 * On supported hardware, debuggable builds make the HID bits read-only
197 * without locking them. This lets people manually modify HID bits while
198 * debugging, since they can use a debugging tool to first reset the HID
199 * bits back to read/write. However it will still catch xnu changes that
200 * accidentally write to HID bits after they've been made read-only.
201 */
202
203#endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */
204