1 | /* |
2 | * Copyright (c) 2007-2016 Apple, Inc. All rights reserved. |
3 | * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. |
4 | * |
5 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
6 | * |
7 | * This file contains Original Code and/or Modifications of Original Code |
8 | * as defined in and that are subject to the Apple Public Source License |
9 | * Version 2.0 (the 'License'). You may not use this file except in |
10 | * compliance with the License. The rights granted to you under the License |
11 | * may not be used to create, or enable the creation or redistribution of, |
12 | * unlawful or unlicensed copies of an Apple operating system, or to |
13 | * circumvent, violate, or enable the circumvention or violation of, any |
14 | * terms of an Apple operating system software license agreement. |
15 | * |
16 | * Please obtain a copy of the License at |
17 | * http://www.opensource.apple.com/apsl/ and read it before using this file. |
18 | * |
19 | * The Original Code and all software distributed under the License are |
20 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER |
21 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
22 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, |
23 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
24 | * Please see the License for the specific language governing rights and |
25 | * limitations under the License. |
26 | * |
27 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
28 | */ |
29 | /* |
30 | * Mach Operating System |
31 | * Copyright (c) 1991,1990,1989,1988,1987 Carnegie Mellon University |
32 | * All Rights Reserved. |
33 | * |
34 | * Permission to use, copy, modify and distribute this software and its |
35 | * documentation is hereby granted, provided that both the copyright |
36 | * notice and this permission notice appear in all copies of the |
37 | * software, derivative works or modified versions, and any portions |
38 | * thereof, and that both notices appear in supporting documentation. |
39 | * |
40 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
41 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR |
42 | * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
43 | * |
44 | * Carnegie Mellon requests users of this software to return to |
45 | * |
46 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
47 | * School of Computer Science |
48 | * Carnegie Mellon University |
49 | * Pittsburgh PA 15213-3890 |
50 | * |
51 | * any improvements or extensions that they make and grant Carnegie Mellon |
52 | * the rights to redistribute these changes. |
53 | */ |
54 | /* File: machine.h |
55 | * Author: Avadis Tevanian, Jr. |
56 | * Date: 1986 |
57 | * |
58 | * Machine independent machine abstraction. |
59 | */ |
60 | |
61 | #ifndef _MACH_MACHINE_H_ |
62 | #define _MACH_MACHINE_H_ |
63 | |
64 | #ifndef __ASSEMBLER__ |
65 | |
66 | #include <stdint.h> |
67 | #include <mach/machine/vm_types.h> |
68 | #include <mach/boolean.h> |
69 | |
70 | typedef integer_t cpu_type_t; |
71 | typedef integer_t cpu_subtype_t; |
72 | typedef integer_t cpu_threadtype_t; |
73 | |
74 | #define CPU_STATE_MAX 4 |
75 | |
76 | #define CPU_STATE_USER 0 |
77 | #define CPU_STATE_SYSTEM 1 |
78 | #define CPU_STATE_IDLE 2 |
79 | #define CPU_STATE_NICE 3 |
80 | |
81 | #ifdef KERNEL_PRIVATE |
82 | |
83 | #include <sys/cdefs.h> |
84 | |
85 | __BEGIN_DECLS |
86 | cpu_type_t cpu_type(void); |
87 | |
88 | cpu_subtype_t cpu_subtype(void); |
89 | |
90 | cpu_threadtype_t cpu_threadtype(void); |
91 | __END_DECLS |
92 | |
93 | #ifdef MACH_KERNEL_PRIVATE |
94 | |
95 | struct machine_info { |
96 | integer_t major_version; /* kernel major version id */ |
97 | integer_t minor_version; /* kernel minor version id */ |
98 | integer_t max_cpus; /* max number of CPUs possible */ |
99 | uint32_t memory_size; /* size of memory in bytes, capped at 2 GB */ |
100 | uint64_t max_mem; /* actual size of physical memory */ |
101 | uint32_t physical_cpu; /* number of physical CPUs now available */ |
102 | integer_t physical_cpu_max; /* max number of physical CPUs possible */ |
103 | uint32_t logical_cpu; /* number of logical cpu now available */ |
104 | integer_t logical_cpu_max; /* max number of physical CPUs possible */ |
105 | }; |
106 | |
107 | typedef struct machine_info *machine_info_t; |
108 | typedef struct machine_info machine_info_data_t; |
109 | |
110 | extern struct machine_info machine_info; |
111 | |
112 | __BEGIN_DECLS |
113 | cpu_type_t slot_type( |
114 | int slot_num); |
115 | |
116 | cpu_subtype_t slot_subtype( |
117 | int slot_num); |
118 | |
119 | cpu_threadtype_t slot_threadtype( |
120 | int slot_num); |
121 | __END_DECLS |
122 | |
123 | #endif /* MACH_KERNEL_PRIVATE */ |
124 | #endif /* KERNEL_PRIVATE */ |
125 | |
126 | |
127 | /* |
128 | * Capability bits used in the definition of cpu_type. |
129 | */ |
130 | #define CPU_ARCH_MASK 0xff000000 /* mask for architecture bits */ |
131 | #define CPU_ARCH_ABI64 0x01000000 /* 64 bit ABI */ |
132 | #define CPU_ARCH_ABI64_32 0x02000000 /* ABI for 64-bit hardware with 32-bit types; LP32 */ |
133 | |
134 | /* |
135 | * Machine types known by all. |
136 | */ |
137 | |
138 | #define CPU_TYPE_ANY ((cpu_type_t) -1) |
139 | |
140 | #define CPU_TYPE_VAX ((cpu_type_t) 1) |
141 | /* skip ((cpu_type_t) 2) */ |
142 | /* skip ((cpu_type_t) 3) */ |
143 | /* skip ((cpu_type_t) 4) */ |
144 | /* skip ((cpu_type_t) 5) */ |
145 | #define CPU_TYPE_MC680x0 ((cpu_type_t) 6) |
146 | #define CPU_TYPE_X86 ((cpu_type_t) 7) |
147 | #define CPU_TYPE_I386 CPU_TYPE_X86 /* compatibility */ |
148 | #define CPU_TYPE_X86_64 (CPU_TYPE_X86 | CPU_ARCH_ABI64) |
149 | |
150 | /* skip CPU_TYPE_MIPS ((cpu_type_t) 8) */ |
151 | /* skip ((cpu_type_t) 9) */ |
152 | #define CPU_TYPE_MC98000 ((cpu_type_t) 10) |
153 | #define CPU_TYPE_HPPA ((cpu_type_t) 11) |
154 | #define CPU_TYPE_ARM ((cpu_type_t) 12) |
155 | #define CPU_TYPE_ARM64 (CPU_TYPE_ARM | CPU_ARCH_ABI64) |
156 | #define CPU_TYPE_ARM64_32 (CPU_TYPE_ARM | CPU_ARCH_ABI64_32) |
157 | #define CPU_TYPE_MC88000 ((cpu_type_t) 13) |
158 | #define CPU_TYPE_SPARC ((cpu_type_t) 14) |
159 | #define CPU_TYPE_I860 ((cpu_type_t) 15) |
160 | /* skip CPU_TYPE_ALPHA ((cpu_type_t) 16) */ |
161 | /* skip ((cpu_type_t) 17) */ |
162 | #define CPU_TYPE_POWERPC ((cpu_type_t) 18) |
163 | #define CPU_TYPE_POWERPC64 (CPU_TYPE_POWERPC | CPU_ARCH_ABI64) |
164 | /* skip ((cpu_type_t) 19) */ |
165 | /* skip ((cpu_type_t) 20 */ |
166 | /* skip ((cpu_type_t) 21 */ |
167 | /* skip ((cpu_type_t) 22 */ |
168 | /* skip ((cpu_type_t) 23 */ |
169 | |
170 | /* |
171 | * Machine subtypes (these are defined here, instead of in a machine |
172 | * dependent directory, so that any program can get all definitions |
173 | * regardless of where is it compiled). |
174 | */ |
175 | |
176 | /* |
177 | * Capability bits used in the definition of cpu_subtype. |
178 | */ |
179 | #define CPU_SUBTYPE_MASK 0xff000000 /* mask for feature flags */ |
180 | #define CPU_SUBTYPE_LIB64 0x80000000 /* 64 bit libraries */ |
181 | #define CPU_SUBTYPE_PTRAUTH_ABI 0x80000000 /* pointer authentication with versioned ABI */ |
182 | |
183 | /* |
184 | * When selecting a slice, ANY will pick the slice with the best |
185 | * grading for the selected cpu_type_t, unlike the "ALL" subtypes, |
186 | * which are the slices that can run on any hardware for that cpu type. |
187 | */ |
188 | #define CPU_SUBTYPE_ANY ((cpu_subtype_t) -1) |
189 | |
190 | /* |
191 | * Object files that are hand-crafted to run on any |
192 | * implementation of an architecture are tagged with |
193 | * CPU_SUBTYPE_MULTIPLE. This functions essentially the same as |
194 | * the "ALL" subtype of an architecture except that it allows us |
195 | * to easily find object files that may need to be modified |
196 | * whenever a new implementation of an architecture comes out. |
197 | * |
198 | * It is the responsibility of the implementor to make sure the |
199 | * software handles unsupported implementations elegantly. |
200 | */ |
201 | #define CPU_SUBTYPE_MULTIPLE ((cpu_subtype_t) -1) |
202 | #define CPU_SUBTYPE_LITTLE_ENDIAN ((cpu_subtype_t) 0) |
203 | #define CPU_SUBTYPE_BIG_ENDIAN ((cpu_subtype_t) 1) |
204 | |
205 | /* |
206 | * Machine threadtypes. |
207 | * This is none - not defined - for most machine types/subtypes. |
208 | */ |
209 | #define CPU_THREADTYPE_NONE ((cpu_threadtype_t) 0) |
210 | |
211 | /* |
212 | * VAX subtypes (these do *not* necessary conform to the actual cpu |
213 | * ID assigned by DEC available via the SID register). |
214 | */ |
215 | |
216 | #define CPU_SUBTYPE_VAX_ALL ((cpu_subtype_t) 0) |
217 | #define CPU_SUBTYPE_VAX780 ((cpu_subtype_t) 1) |
218 | #define CPU_SUBTYPE_VAX785 ((cpu_subtype_t) 2) |
219 | #define CPU_SUBTYPE_VAX750 ((cpu_subtype_t) 3) |
220 | #define CPU_SUBTYPE_VAX730 ((cpu_subtype_t) 4) |
221 | #define CPU_SUBTYPE_UVAXI ((cpu_subtype_t) 5) |
222 | #define CPU_SUBTYPE_UVAXII ((cpu_subtype_t) 6) |
223 | #define CPU_SUBTYPE_VAX8200 ((cpu_subtype_t) 7) |
224 | #define CPU_SUBTYPE_VAX8500 ((cpu_subtype_t) 8) |
225 | #define CPU_SUBTYPE_VAX8600 ((cpu_subtype_t) 9) |
226 | #define CPU_SUBTYPE_VAX8650 ((cpu_subtype_t) 10) |
227 | #define CPU_SUBTYPE_VAX8800 ((cpu_subtype_t) 11) |
228 | #define CPU_SUBTYPE_UVAXIII ((cpu_subtype_t) 12) |
229 | |
230 | /* |
231 | * 680x0 subtypes |
232 | * |
233 | * The subtype definitions here are unusual for historical reasons. |
234 | * NeXT used to consider 68030 code as generic 68000 code. For |
235 | * backwards compatability: |
236 | * |
237 | * CPU_SUBTYPE_MC68030 symbol has been preserved for source code |
238 | * compatability. |
239 | * |
240 | * CPU_SUBTYPE_MC680x0_ALL has been defined to be the same |
241 | * subtype as CPU_SUBTYPE_MC68030 for binary comatability. |
242 | * |
243 | * CPU_SUBTYPE_MC68030_ONLY has been added to allow new object |
244 | * files to be tagged as containing 68030-specific instructions. |
245 | */ |
246 | |
247 | #define CPU_SUBTYPE_MC680x0_ALL ((cpu_subtype_t) 1) |
248 | #define CPU_SUBTYPE_MC68030 ((cpu_subtype_t) 1) /* compat */ |
249 | #define CPU_SUBTYPE_MC68040 ((cpu_subtype_t) 2) |
250 | #define CPU_SUBTYPE_MC68030_ONLY ((cpu_subtype_t) 3) |
251 | |
252 | /* |
253 | * I386 subtypes |
254 | */ |
255 | |
256 | #define CPU_SUBTYPE_INTEL(f, m) ((cpu_subtype_t) (f) + ((m) << 4)) |
257 | |
258 | #define CPU_SUBTYPE_I386_ALL CPU_SUBTYPE_INTEL(3, 0) |
259 | #define CPU_SUBTYPE_386 CPU_SUBTYPE_INTEL(3, 0) |
260 | #define CPU_SUBTYPE_486 CPU_SUBTYPE_INTEL(4, 0) |
261 | #define CPU_SUBTYPE_486SX CPU_SUBTYPE_INTEL(4, 8) // 8 << 4 = 128 |
262 | #define CPU_SUBTYPE_586 CPU_SUBTYPE_INTEL(5, 0) |
263 | #define CPU_SUBTYPE_PENT CPU_SUBTYPE_INTEL(5, 0) |
264 | #define CPU_SUBTYPE_PENTPRO CPU_SUBTYPE_INTEL(6, 1) |
265 | #define CPU_SUBTYPE_PENTII_M3 CPU_SUBTYPE_INTEL(6, 3) |
266 | #define CPU_SUBTYPE_PENTII_M5 CPU_SUBTYPE_INTEL(6, 5) |
267 | #define CPU_SUBTYPE_CELERON CPU_SUBTYPE_INTEL(7, 6) |
268 | #define CPU_SUBTYPE_CELERON_MOBILE CPU_SUBTYPE_INTEL(7, 7) |
269 | #define CPU_SUBTYPE_PENTIUM_3 CPU_SUBTYPE_INTEL(8, 0) |
270 | #define CPU_SUBTYPE_PENTIUM_3_M CPU_SUBTYPE_INTEL(8, 1) |
271 | #define CPU_SUBTYPE_PENTIUM_3_XEON CPU_SUBTYPE_INTEL(8, 2) |
272 | #define CPU_SUBTYPE_PENTIUM_M CPU_SUBTYPE_INTEL(9, 0) |
273 | #define CPU_SUBTYPE_PENTIUM_4 CPU_SUBTYPE_INTEL(10, 0) |
274 | #define CPU_SUBTYPE_PENTIUM_4_M CPU_SUBTYPE_INTEL(10, 1) |
275 | #define CPU_SUBTYPE_ITANIUM CPU_SUBTYPE_INTEL(11, 0) |
276 | #define CPU_SUBTYPE_ITANIUM_2 CPU_SUBTYPE_INTEL(11, 1) |
277 | #define CPU_SUBTYPE_XEON CPU_SUBTYPE_INTEL(12, 0) |
278 | #define CPU_SUBTYPE_XEON_MP CPU_SUBTYPE_INTEL(12, 1) |
279 | |
280 | #define CPU_SUBTYPE_INTEL_FAMILY(x) ((x) & 15) |
281 | #define CPU_SUBTYPE_INTEL_FAMILY_MAX 15 |
282 | |
283 | #define CPU_SUBTYPE_INTEL_MODEL(x) ((x) >> 4) |
284 | #define CPU_SUBTYPE_INTEL_MODEL_ALL 0 |
285 | |
286 | /* |
287 | * X86 subtypes. |
288 | */ |
289 | |
290 | #define CPU_SUBTYPE_X86_ALL ((cpu_subtype_t)3) |
291 | #define CPU_SUBTYPE_X86_64_ALL ((cpu_subtype_t)3) |
292 | #define CPU_SUBTYPE_X86_ARCH1 ((cpu_subtype_t)4) |
293 | #define CPU_SUBTYPE_X86_64_H ((cpu_subtype_t)8) /* Haswell feature subset */ |
294 | |
295 | |
296 | #define CPU_THREADTYPE_INTEL_HTT ((cpu_threadtype_t) 1) |
297 | |
298 | /* |
299 | * Mips subtypes. |
300 | */ |
301 | |
302 | #define CPU_SUBTYPE_MIPS_ALL ((cpu_subtype_t) 0) |
303 | #define CPU_SUBTYPE_MIPS_R2300 ((cpu_subtype_t) 1) |
304 | #define CPU_SUBTYPE_MIPS_R2600 ((cpu_subtype_t) 2) |
305 | #define CPU_SUBTYPE_MIPS_R2800 ((cpu_subtype_t) 3) |
306 | #define CPU_SUBTYPE_MIPS_R2000a ((cpu_subtype_t) 4) /* pmax */ |
307 | #define CPU_SUBTYPE_MIPS_R2000 ((cpu_subtype_t) 5) |
308 | #define CPU_SUBTYPE_MIPS_R3000a ((cpu_subtype_t) 6) /* 3max */ |
309 | #define CPU_SUBTYPE_MIPS_R3000 ((cpu_subtype_t) 7) |
310 | |
311 | /* |
312 | * MC98000 (PowerPC) subtypes |
313 | */ |
314 | #define CPU_SUBTYPE_MC98000_ALL ((cpu_subtype_t) 0) |
315 | #define CPU_SUBTYPE_MC98601 ((cpu_subtype_t) 1) |
316 | |
317 | /* |
318 | * HPPA subtypes for Hewlett-Packard HP-PA family of |
319 | * risc processors. Port by NeXT to 700 series. |
320 | */ |
321 | |
322 | #define CPU_SUBTYPE_HPPA_ALL ((cpu_subtype_t) 0) |
323 | #define CPU_SUBTYPE_HPPA_7100 ((cpu_subtype_t) 0) /* compat */ |
324 | #define CPU_SUBTYPE_HPPA_7100LC ((cpu_subtype_t) 1) |
325 | |
326 | /* |
327 | * MC88000 subtypes. |
328 | */ |
329 | #define CPU_SUBTYPE_MC88000_ALL ((cpu_subtype_t) 0) |
330 | #define CPU_SUBTYPE_MC88100 ((cpu_subtype_t) 1) |
331 | #define CPU_SUBTYPE_MC88110 ((cpu_subtype_t) 2) |
332 | |
333 | /* |
334 | * SPARC subtypes |
335 | */ |
336 | #define CPU_SUBTYPE_SPARC_ALL ((cpu_subtype_t) 0) |
337 | |
338 | /* |
339 | * I860 subtypes |
340 | */ |
341 | #define CPU_SUBTYPE_I860_ALL ((cpu_subtype_t) 0) |
342 | #define CPU_SUBTYPE_I860_860 ((cpu_subtype_t) 1) |
343 | |
344 | /* |
345 | * PowerPC subtypes |
346 | */ |
347 | #define CPU_SUBTYPE_POWERPC_ALL ((cpu_subtype_t) 0) |
348 | #define CPU_SUBTYPE_POWERPC_601 ((cpu_subtype_t) 1) |
349 | #define CPU_SUBTYPE_POWERPC_602 ((cpu_subtype_t) 2) |
350 | #define CPU_SUBTYPE_POWERPC_603 ((cpu_subtype_t) 3) |
351 | #define CPU_SUBTYPE_POWERPC_603e ((cpu_subtype_t) 4) |
352 | #define CPU_SUBTYPE_POWERPC_603ev ((cpu_subtype_t) 5) |
353 | #define CPU_SUBTYPE_POWERPC_604 ((cpu_subtype_t) 6) |
354 | #define CPU_SUBTYPE_POWERPC_604e ((cpu_subtype_t) 7) |
355 | #define CPU_SUBTYPE_POWERPC_620 ((cpu_subtype_t) 8) |
356 | #define CPU_SUBTYPE_POWERPC_750 ((cpu_subtype_t) 9) |
357 | #define CPU_SUBTYPE_POWERPC_7400 ((cpu_subtype_t) 10) |
358 | #define CPU_SUBTYPE_POWERPC_7450 ((cpu_subtype_t) 11) |
359 | #define CPU_SUBTYPE_POWERPC_970 ((cpu_subtype_t) 100) |
360 | |
361 | /* |
362 | * ARM subtypes |
363 | */ |
364 | #define CPU_SUBTYPE_ARM_ALL ((cpu_subtype_t) 0) |
365 | #define CPU_SUBTYPE_ARM_V4T ((cpu_subtype_t) 5) |
366 | #define CPU_SUBTYPE_ARM_V6 ((cpu_subtype_t) 6) |
367 | #define CPU_SUBTYPE_ARM_V5TEJ ((cpu_subtype_t) 7) |
368 | #define CPU_SUBTYPE_ARM_XSCALE ((cpu_subtype_t) 8) |
369 | #define CPU_SUBTYPE_ARM_V7 ((cpu_subtype_t) 9) /* ARMv7-A and ARMv7-R */ |
370 | #define CPU_SUBTYPE_ARM_V7F ((cpu_subtype_t) 10) /* Cortex A9 */ |
371 | #define CPU_SUBTYPE_ARM_V7S ((cpu_subtype_t) 11) /* Swift */ |
372 | #define CPU_SUBTYPE_ARM_V7K ((cpu_subtype_t) 12) |
373 | #define CPU_SUBTYPE_ARM_V8 ((cpu_subtype_t) 13) |
374 | #define CPU_SUBTYPE_ARM_V6M ((cpu_subtype_t) 14) /* Not meant to be run under xnu */ |
375 | #define CPU_SUBTYPE_ARM_V7M ((cpu_subtype_t) 15) /* Not meant to be run under xnu */ |
376 | #define CPU_SUBTYPE_ARM_V7EM ((cpu_subtype_t) 16) /* Not meant to be run under xnu */ |
377 | #define CPU_SUBTYPE_ARM_V8M ((cpu_subtype_t) 17) /* Not meant to be run under xnu */ |
378 | |
379 | /* |
380 | * ARM64 subtypes |
381 | */ |
382 | #define CPU_SUBTYPE_ARM64_ALL ((cpu_subtype_t) 0) |
383 | #define CPU_SUBTYPE_ARM64_V8 ((cpu_subtype_t) 1) |
384 | #define CPU_SUBTYPE_ARM64E ((cpu_subtype_t) 2) |
385 | |
386 | /* CPU subtype feature flags for ptrauth on arm64e platforms */ |
387 | #define CPU_SUBTYPE_ARM64_PTR_AUTH_MASK 0x0f000000 |
388 | #define CPU_SUBTYPE_ARM64_PTR_AUTH_VERSION(x) (((x) & CPU_SUBTYPE_ARM64_PTR_AUTH_MASK) >> 24) |
389 | #ifdef PRIVATE |
390 | #define CPU_SUBTYPE_ARM64_PTR_AUTH_CURRENT_VERSION 0 |
391 | #endif /* PRIVATE */ |
392 | |
393 | /* |
394 | * ARM64_32 subtypes |
395 | */ |
396 | #define CPU_SUBTYPE_ARM64_32_ALL ((cpu_subtype_t) 0) |
397 | #define CPU_SUBTYPE_ARM64_32_V8 ((cpu_subtype_t) 1) |
398 | |
399 | #endif /* !__ASSEMBLER__ */ |
400 | |
401 | /* |
402 | * CPU families (sysctl hw.cpufamily) |
403 | * |
404 | * These are meant to identify the CPU's marketing name - an |
405 | * application can map these to (possibly) localized strings. |
406 | * NB: the encodings of the CPU families are intentionally arbitrary. |
407 | * There is no ordering, and you should never try to deduce whether |
408 | * or not some feature is available based on the family. |
409 | * Use feature flags (eg, hw.optional.altivec) to test for optional |
410 | * functionality. |
411 | */ |
412 | #define CPUFAMILY_UNKNOWN 0 |
413 | #define CPUFAMILY_POWERPC_G3 0xcee41549 |
414 | #define CPUFAMILY_POWERPC_G4 0x77c184ae |
415 | #define CPUFAMILY_POWERPC_G5 0xed76d8aa |
416 | #define CPUFAMILY_INTEL_6_13 0xaa33392b |
417 | #define CPUFAMILY_INTEL_PENRYN 0x78ea4fbc |
418 | #define CPUFAMILY_INTEL_NEHALEM 0x6b5a4cd2 |
419 | #define CPUFAMILY_INTEL_WESTMERE 0x573b5eec |
420 | #define CPUFAMILY_INTEL_SANDYBRIDGE 0x5490b78c |
421 | #define CPUFAMILY_INTEL_IVYBRIDGE 0x1f65e835 |
422 | #define CPUFAMILY_INTEL_HASWELL 0x10b282dc |
423 | #define CPUFAMILY_INTEL_BROADWELL 0x582ed09c |
424 | #define CPUFAMILY_INTEL_SKYLAKE 0x37fc219f |
425 | #define CPUFAMILY_INTEL_KABYLAKE 0x0f817246 |
426 | #define CPUFAMILY_INTEL_ICELAKE 0x38435547 |
427 | #define CPUFAMILY_INTEL_COMETLAKE 0x1cf8a03e |
428 | #define CPUFAMILY_ARM_9 0xe73283ae |
429 | #define CPUFAMILY_ARM_11 0x8ff620d8 |
430 | #define CPUFAMILY_ARM_XSCALE 0x53b005f5 |
431 | #define CPUFAMILY_ARM_12 0xbd1b0ae9 |
432 | #define CPUFAMILY_ARM_13 0x0cc90e64 |
433 | #define CPUFAMILY_ARM_14 0x96077ef1 |
434 | #define CPUFAMILY_ARM_15 0xa8511bca |
435 | #define CPUFAMILY_ARM_SWIFT 0x1e2d6381 |
436 | #define CPUFAMILY_ARM_CYCLONE 0x37a09642 |
437 | #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e |
438 | #define CPUFAMILY_ARM_TWISTER 0x92fb37c8 |
439 | #define CPUFAMILY_ARM_HURRICANE 0x67ceee93 |
440 | #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6 |
441 | #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f |
442 | #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2 |
443 | #ifndef RC_HIDE_XNU_FIRESTORM |
444 | #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3 |
445 | #endif /* !RC_HIDE_XNU_FIRESTORM */ |
446 | |
447 | /* Described in rdar://64125549 */ |
448 | #define CPUSUBFAMILY_UNKNOWN 0 |
449 | #define CPUSUBFAMILY_ARM_HP 1 |
450 | #define CPUSUBFAMILY_ARM_HG 2 |
451 | #define CPUSUBFAMILY_ARM_M 3 |
452 | #define CPUSUBFAMILY_ARM_HS 4 |
453 | #define CPUSUBFAMILY_ARM_HC_HD 5 |
454 | #define CPUSUBFAMILY_ARM_HA 6 |
455 | |
456 | /* The following synonyms are deprecated: */ |
457 | #define CPUFAMILY_INTEL_6_23 CPUFAMILY_INTEL_PENRYN |
458 | #define CPUFAMILY_INTEL_6_26 CPUFAMILY_INTEL_NEHALEM |
459 | |
460 | |
461 | #endif /* _MACH_MACHINE_H_ */ |
462 | |