1 | /* |
2 | * Copyright (c) 2007-2016 Apple Inc. All rights reserved. |
3 | * |
4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
5 | * |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License |
8 | * Version 2.0 (the 'License'). You may not use this file except in |
9 | * compliance with the License. The rights granted to you under the License |
10 | * may not be used to create, or enable the creation or redistribution of, |
11 | * unlawful or unlicensed copies of an Apple operating system, or to |
12 | * circumvent, violate, or enable the circumvention or violation of, any |
13 | * terms of an Apple operating system software license agreement. |
14 | * |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. |
17 | * |
18 | * The Original Code and all software distributed under the License are |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and |
24 | * limitations under the License. |
25 | * |
26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
27 | */ |
28 | /* |
29 | * @OSF_COPYRIGHT@ |
30 | */ |
31 | |
32 | /* |
33 | * ARM CPU identification |
34 | */ |
35 | |
36 | #ifndef _MACHINE_CPUID_H_ |
37 | #define _MACHINE_CPUID_H_ |
38 | |
39 | #include <stdint.h> |
40 | #include <mach/boolean.h> |
41 | #include <machine/machine_cpuid.h> |
42 | |
43 | typedef struct { |
44 | uint32_t arm_rev : 4, /* 00:03 revision number */ |
45 | arm_part : 12, /* 04:15 primary part number */ |
46 | arm_arch : 4, /* 16:19 architecture */ |
47 | arm_variant : 4, /* 20:23 variant */ |
48 | arm_implementor : 8; /* 24:31 implementor (0x41) */ |
49 | } arm_cpuid_bits_t; |
50 | |
51 | typedef union { |
52 | arm_cpuid_bits_t arm_info; /* ARM9xx, ARM11xx, and later processors */ |
53 | uint32_t value; |
54 | } arm_cpu_info_t; |
55 | |
56 | /* Implementor codes */ |
57 | #define CPU_VID_ARM 0x41 // ARM Limited |
58 | #define CPU_VID_DEC 0x44 // Digital Equipment Corporation |
59 | #define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc. |
60 | #define CPU_VID_MARVELL 0x56 // Marvell Semiconductor Inc. |
61 | #define CPU_VID_INTEL 0x69 // Intel ARM parts. |
62 | #define CPU_VID_APPLE 0x61 // Apple Inc. |
63 | |
64 | |
65 | /* ARM Architecture Codes */ |
66 | |
67 | #define CPU_ARCH_ARMv4 0x1 /* ARMv4 */ |
68 | #define CPU_ARCH_ARMv4T 0x2 /* ARMv4 + Thumb */ |
69 | #define CPU_ARCH_ARMv5 0x3 /* ARMv5 */ |
70 | #define CPU_ARCH_ARMv5T 0x4 /* ARMv5 + Thumb */ |
71 | #define CPU_ARCH_ARMv5TE 0x5 /* ARMv5 + Thumb + Extensions(?) */ |
72 | #define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */ |
73 | #define CPU_ARCH_ARMv6 0x7 /* ARMv6 */ |
74 | #define CPU_ARCH_ARMv7 0x8 /* ARMv7 */ |
75 | #define CPU_ARCH_ARMv7f 0x9 /* ARMv7 for Cortex A9 */ |
76 | #define CPU_ARCH_ARMv7s 0xa /* ARMv7 for Swift */ |
77 | #define CPU_ARCH_ARMv7k 0xb /* ARMv7 for Cortex A7 */ |
78 | |
79 | #define CPU_ARCH_ARMv8 0xc /* Subtype for CPU_TYPE_ARM64 */ |
80 | |
81 | |
82 | /* special code indicating we need to look somewhere else for the architecture version */ |
83 | #define CPU_ARCH_EXTENDED 0xF |
84 | |
85 | /* ARM Part Numbers */ |
86 | /* |
87 | * XXX: ARM Todo |
88 | * Fill out these part numbers more completely |
89 | */ |
90 | |
91 | /* ARM9 (ARMv4T architecture) */ |
92 | #define CPU_PART_920T 0x920 |
93 | #define CPU_PART_926EJS 0x926 /* ARM926EJ-S */ |
94 | |
95 | /* ARM11 (ARMv6 architecture) */ |
96 | #define CPU_PART_1136JFS 0xB36 /* ARM1136JF-S or ARM1136J-S */ |
97 | #define CPU_PART_1176JZFS 0xB76 /* ARM1176JZF-S */ |
98 | |
99 | /* G1 (ARMv7 architecture) */ |
100 | #define CPU_PART_CORTEXA5 0xC05 |
101 | |
102 | /* M7 (ARMv7 architecture) */ |
103 | #define CPU_PART_CORTEXA7 0xC07 |
104 | |
105 | /* H2 H3 (ARMv7 architecture) */ |
106 | #define CPU_PART_CORTEXA8 0xC08 |
107 | |
108 | /* H4 (ARMv7 architecture) */ |
109 | #define CPU_PART_CORTEXA9 0xC09 |
110 | |
111 | /* H5 (SWIFT architecture) */ |
112 | #define CPU_PART_SWIFT 0x0 |
113 | |
114 | /* H6 (ARMv8 architecture) */ |
115 | #define CPU_PART_CYCLONE 0x1 |
116 | |
117 | /* H7 (ARMv8 architecture) */ |
118 | #define CPU_PART_TYPHOON 0x2 |
119 | |
120 | /* H7G (ARMv8 architecture) */ |
121 | #define CPU_PART_TYPHOON_CAPRI 0x3 |
122 | |
123 | /* H8 (ARMv8 architecture) */ |
124 | #define CPU_PART_TWISTER 0x4 |
125 | |
126 | /* H8G H8M (ARMv8 architecture) */ |
127 | #define CPU_PART_TWISTER_ELBA_MALTA 0x5 |
128 | |
129 | /* H9 (ARMv8 architecture) */ |
130 | #define CPU_PART_HURRICANE 0x6 |
131 | |
132 | /* H9G (ARMv8 architecture) */ |
133 | #define CPU_PART_HURRICANE_MYST 0x7 |
134 | |
135 | /* H10 p-Core (ARMv8 architecture) */ |
136 | #define CPU_PART_MONSOON 0x8 |
137 | |
138 | /* H10 e-Core (ARMv8 architecture) */ |
139 | #define CPU_PART_MISTRAL 0x9 |
140 | |
141 | |
142 | /* Cache type identification */ |
143 | |
144 | /* Supported Cache Types */ |
145 | typedef enum { |
146 | CACHE_WRITE_THROUGH, |
147 | CACHE_WRITE_BACK, |
148 | CACHE_READ_ALLOCATION, |
149 | CACHE_WRITE_ALLOCATION, |
150 | CACHE_UNKNOWN |
151 | } cache_type_t; |
152 | |
153 | typedef struct { |
154 | boolean_t c_unified; /* unified I & D cache? */ |
155 | uint32_t c_isize; /* in Bytes (ARM caches can be 0.5 KB) */ |
156 | boolean_t c_i_ppage; /* protected page restriction for I cache |
157 | * (see B6-11 in ARM DDI 0100I document). */ |
158 | uint32_t c_dsize; /* in Bytes (ARM caches can be 0.5 KB) */ |
159 | boolean_t c_d_ppage; /* protected page restriction for I cache |
160 | * (see B6-11 in ARM DDI 0100I document). */ |
161 | cache_type_t c_type; /* WB or WT */ |
162 | uint32_t c_linesz; /* number of bytes */ |
163 | uint32_t c_assoc; /* n-way associativity */ |
164 | uint32_t c_l2size; /* L2 size, if present */ |
165 | uint32_t c_bulksize_op; /* bulk operation size limit. 0 if disabled */ |
166 | uint32_t c_inner_cache_size; /* inner dache size */ |
167 | } cache_info_t; |
168 | |
169 | typedef struct { |
170 | uint32_t |
171 | |
172 | RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */ |
173 | SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */ |
174 | DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */ |
175 | TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */ |
176 | D:4, /* 19:16 - VFP hardware divide supported: 0x1 */ |
177 | SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */ |
178 | SV:4, /* 27:24 - VFP short vector supported: 0x1 */ |
179 | RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */ |
180 | } arm_mvfr0_t; |
181 | |
182 | typedef union { |
183 | arm_mvfr0_t bits; |
184 | uint32_t value; |
185 | } arm_mvfr0_info_t; |
186 | |
187 | typedef struct { |
188 | uint32_t |
189 | |
190 | FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */ |
191 | DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */ |
192 | LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */ |
193 | I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */ |
194 | SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */ |
195 | HPFP:4, /* 23:20 - Half precision floating-point instructions supported */ |
196 | RSVP:8; /* 31:24 - Reserved */ |
197 | } arm_mvfr1_t; |
198 | |
199 | typedef union { |
200 | arm_mvfr1_t bits; |
201 | uint32_t value; |
202 | } arm_mvfr1_info_t; |
203 | |
204 | typedef struct { |
205 | uint32_t neon; |
206 | uint32_t neon_hpfp; |
207 | uint32_t neon_fp16; |
208 | } arm_mvfp_info_t; |
209 | |
210 | #ifdef __cplusplus |
211 | extern "C" { |
212 | #endif |
213 | |
214 | extern void do_cpuid(void); |
215 | extern arm_cpu_info_t *cpuid_info(void); |
216 | extern int cpuid_get_cpufamily(void); |
217 | |
218 | extern void do_debugid(void); |
219 | extern arm_debug_info_t *arm_debug_info(void); |
220 | |
221 | extern void do_cacheid(void); |
222 | extern cache_info_t *cache_info(void); |
223 | |
224 | extern void do_mvfpid(void); |
225 | extern arm_mvfp_info_t *arm_mvfp_info(void); |
226 | |
227 | #ifdef __cplusplus |
228 | } |
229 | #endif |
230 | |
231 | #endif // _MACHINE_CPUID_H_ |
232 | |