1/*
2 * Copyright (c) 2012-2015 Apple Inc. All rights reserved.
3 */
4
5#ifndef _PEXPERT_ARM64_COMMON_H
6#define _PEXPERT_ARM64_COMMON_H
7
8#ifdef APPLE_ARM64_ARCH_FAMILY
9
10#define ARM64_REG_HID0 S3_0_c15_c0_0
11#define ARM64_REG_HID0_LoopBuffDisb (1<<20)
12#define ARM64_REG_HID0_ICPrefLimitOneBrn (1<<25)
13#define ARM64_REG_HID0_PMULLFuseDisable (1ULL<<33)
14#define ARM64_REG_HID0_ICPrefDepth_bshift 60
15#define ARM64_REG_HID0_ICPrefDepth_bmsk (7ULL <<ARM64_REG_HID0_ICPrefDepth_bshift)
16
17#define ARM64_REG_EHID0 S3_0_c15_c0_1
18#define ARM64_REG_EHID0_nfpRetFwdDisb (1ULL<<45)
19
20#define ARM64_REG_HID1 S3_0_c15_c1_0
21#define ARM64_REG_HID1_disCmpBrFusion (1<<14)
22#define ARM64_REG_HID1_rccForceAllIexL3ClksOn (1<<23)
23#define ARM64_REG_HID1_rccDisStallInactiveIexCtl (1<<24)
24#define ARM64_REG_HID1_disLspFlushWithContextSwitch (1<<25)
25#define ARM64_REG_HID1_disAESFuseAcrossGrp (1<<44)
26#define ARM64_REG_HID1_enaBrKillLimit (1ULL << 60)
27
28#define ARM64_REG_HID2 S3_0_c15_c2_0
29#define ARM64_REG_HID2_disMMUmtlbPrefetch (1<<13)
30
31#define ARM64_REG_HID3 S3_0_c15_c3_0
32#define ARM64_REG_HID3_DisDcZvaCmdOnly (1<<25)
33#define ARM64_REG_HID3_DisXmonSnpEvictTriggerL2StarvationMode (1<<54)
34#define ARM64_REG_HID3_DisColorOpt (1<<2)
35
36#define ARM64_REG_EHID3 S3_0_c15_c3_1
37#define ARM64_REG_EHID3_DisColorOpt (1<<2)
38#define ARM64_REG_EHID3_DisDcZvaCmdOnly (1<<25)
39
40#define ARM64_REG_HID4 S3_0_c15_c4_0
41#define ARM64_REG_EHID4 S3_0_c15_c4_1
42
43#define ARM64_REG_HID4_DisDcMVAOps (1<<11)
44#define ARM64_REG_HID4_DisSpecLnchRead (1<<33)
45#define ARM64_REG_HID4_ForceNsOrdLdReqNoOlderLd (1<<39)
46#define ARM64_REG_HID4_DisDcSWL2Ops (1<<44)
47
48#define ARM64_REG_HID5 S3_0_c15_c5_0
49#define ARM64_REG_HID5_DisHwpLd (1<<44)
50#define ARM64_REG_HID5_DisHwpSt (1<<45)
51#define ARM64_REG_HID5_DisFullLineWr (1ULL << 57)
52#define ARM64_REG_HID5_EnableDnFIFORdStall (1ULL << 54)
53#define ARM64_REG_HID5_CrdEdbSnpRsvd_mask (3ULL << 14)
54#define ARM64_REG_HID5_CrdEdbSnpRsvd_VALUE (2ULL << 14)
55
56#define ARM64_REG_EHID5 S3_0_c15_c5_1
57#define ARM64_REG_EHID5_DisFillByp (1 << 35)
58
59#define ARM64_REG_HID6 S3_0_c15_c6_0
60#define ARM64_REG_HID6_DisClkDivGating (1ULL << 55)
61
62#define ARM64_REG_HID7 S3_0_c15_c7_0
63#define ARM64_REG_HID7_disNexFastFmul (1 << 10)
64#define ARM64_REG_HID7_disCrossPick2 (1ULL << 7)
65
66#define ARM64_REG_HID8 S3_0_c15_c8_0
67#define ARM64_REG_HID8_DataSetID0_VALUE (0xF << 4)
68#define ARM64_REG_HID8_DataSetID1_VALUE (0xF << 8)
69#define ARM64_REG_HID8_WkeForceStrictOrder (0x1ULL << 35)
70#define ARM64_REG_HID8_DataSetID2_VALUE (0xF << 56)
71#define ARM64_REG_HID8_DataSetID3_VALUE (0xF << 60)
72
73#define ARM64_REG_HID9 S3_0_c15_c9_0
74
75#define ARM64_REG_HID10 S3_0_c15_c10_0
76#define ARM64_REG_HID10_DisHwpGups (1ULL << 0)
77
78#define ARM64_REG_EHID10 S3_0_c15_c10_1
79#define ARM64_REG_EHID10_rccDisPwrSavePrfClkOff (1ULL << 19)
80
81#if defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER)
82#define ARM64_REG_HID11 S3_0_c15_c13_0
83#else
84#define ARM64_REG_HID11 S3_0_c15_c11_0
85#endif
86#define ARM64_REG_HID11_DisX64NTLnchOpt (1ULL << 1)
87#define ARM64_REG_HID11_DisFillC1BubOpt (1<<7)
88#define ARM64_REG_HID11_DisFastDrainOpt (1ULL << 23)
89
90#define ARM64_REG_EHID11 S3_0_c15_c11_1
91#define ARM64_REG_EHID11_SmbDrainThresh_mask (3ULL << 40)
92
93#if defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER)
94#define ARM64_REG_CYC_CFG S3_5_c15_c4_0
95#define ARM64_REG_CYC_CFG_skipInit (1ULL<<30)
96#define ARM64_REG_CYC_CFG_deepSleep (1ULL<<24)
97#else
98#define ARM64_REG_ACC_OVRD S3_5_c15_c6_0
99#if defined(APPLEMONSOON)
100#define ARM64_REG_ACC_EBLK_OVRD S3_5_c15_c6_1 // EBLK_OVRD on Zephyr
101#endif
102#define ARM64_REG_ACC_OVRD_enDeepSleep (1ULL << 34)
103#define ARM64_REG_ACC_OVRD_disPioOnWfiCpu (1ULL << 32)
104#define ARM64_REG_ACC_OVRD_dsblClkDtr (1ULL << 29)
105#define ARM64_REG_ACC_OVRD_cpmWakeUp_mask (3ULL << 27)
106#define ARM64_REG_ACC_OVRD_cpmWakeUp_force (3ULL << 27)
107#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_mask (3ULL << 25)
108#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deny (2ULL << 25)
109#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deepsleep (3ULL << 25)
110#define ARM64_REG_ACC_OVRD_ok2TrDnLnk_mask (3ULL << 17)
111#define ARM64_REG_ACC_OVRD_ok2TrDnLnk_deepsleep (3ULL << 17)
112#define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_mask (3ULL << 15)
113#define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_deepsleep (2ULL << 15)
114#define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_mask (3ULL << 13)
115#define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_deepsleep (3ULL << 13)
116#endif
117
118#define ARM64_REG_CYC_OVRD S3_5_c15_c5_0
119#define ARM64_REG_CYC_OVRD_ok2pwrdn_force_up (2<<24)
120#define ARM64_REG_CYC_OVRD_ok2pwrdn_force_down (3<<24)
121#define ARM64_REG_CYC_OVRD_disWfiRetn (1<<0)
122
123#if defined(APPLEMONSOON)
124#define ARM64_REG_CYC_OVRD_dsblSnoopTime_mask (3ULL << 30)
125#define ARM64_REG_CYC_OVRD_dsblSnoopPTime (1ULL << 31) /// Don't fetch the timebase from the P-block
126#endif /* APPLEMONSOON */
127
128#define ARM64_REG_LSU_ERR_STS S3_3_c15_c0_0
129#define ARM64_REG_LSU_ERR_STS_L1DTlbMultiHitEN (1ULL<<54)
130
131#define ARM64_REG_E_LSU_ERR_STS S3_3_c15_c2_0
132
133#define ARM64_REG_LSU_ERR_CTL S3_3_c15_c1_0
134#define ARM64_REG_LSU_ERR_CTL_L1DTlbMultiHitEN (1ULL<<3)
135
136#define ARM64_REG_FED_ERR_STS S3_4_C15_C0_0
137
138#define ARM64_REG_E_FED_ERR_STS S3_4_C15_C0_2
139
140#define ARM64_REG_MMU_ERR_STS S3_6_c15_c0_0
141
142#define ARM64_REG_E_MMU_ERR_STS s3_6_c15_c2_0
143
144#define ARM64_REG_L2C_ERR_STS S3_3_c15_c8_0
145
146#define ARM64_REG_L2C_ERR_ADR S3_3_c15_c9_0
147
148#define ARM64_REG_L2C_ERR_INF S3_3_c15_c10_0
149
150#define ARM64_REG_MIGSTS_EL1 S3_4_c15_c0_4
151
152#if defined(HAS_KTRR)
153
154#ifdef ASSEMBLER
155#define ARM64_REG_KTRR_LOWER_EL1 S3_4_c15_c2_3
156#define ARM64_REG_KTRR_UPPER_EL1 S3_4_c15_c2_4
157#define ARM64_REG_KTRR_LOCK_EL1 S3_4_c15_c2_2
158#else
159#define ARM64_REG_KTRR_LOWER_EL1 "S3_4_c15_c2_3"
160#define ARM64_REG_KTRR_UPPER_EL1 "S3_4_c15_c2_4"
161#define ARM64_REG_KTRR_LOCK_EL1 "S3_4_c15_c2_2"
162#endif /* ASSEMBLER */
163
164#endif /* defined (HAS_KTRR) */
165
166
167
168
169#endif /* APPLE_ARM64_ARCH_FAMILY */
170
171
172
173
174
175#define MPIDR_PNE_SHIFT 16 // pcore not ecore
176#define MPIDR_PNE (1 << MPIDR_PNE_SHIFT)
177
178#ifdef ASSEMBLER
179
180/*
181 * arg0: register in which to store result
182 * 0=>not a p-core, non-zero=>p-core
183 */
184.macro ARM64_IS_PCORE
185#if defined(APPLEMONSOON) || HAS_CLUSTER
186 mrs $0, MPIDR_EL1
187 and $0, $0, #(MPIDR_PNE)
188#endif
189.endmacro
190
191/*
192 * reads a special purpose register, using a different msr for e- vs. p-cores
193 * arg0: register indicating the current core type, see ARM64_IS_PCORE
194 * arg1: register in which to store the result of the read
195 * arg2: SPR to use for e-core
196 * arg3: SPR to use for p-core or non-AMP architecture
197 */
198.macro ARM64_READ_EP_SPR
199#if defined(APPLEMONSOON) || HAS_CLUSTER
200 cbnz $0, 1f
201// e-core
202 mrs $1, $2
203 b 2f
204// p-core
2051:
206#endif
207 mrs $1, $3
2082:
209.endmacro
210
211/*
212 * writes a special purpose register, using a different msr for e- vs. p-cores
213 * arg0: register indicating the current core type, see ARM64_IS_PCORE
214 * arg1: register containing the value to write
215 * arg2: SPR to use for e-core
216 * arg3: SPR to use for p-core or non-AMP architecture
217 */
218.macro ARM64_WRITE_EP_SPR
219#if defined(APPLEMONSOON) || HAS_CLUSTER
220 cbnz $0, 1f
221// e-core
222 msr $2, $1
223 b 2f
224// p-core
2251:
226#endif
227 msr $3, $1
2282:
229.endmacro
230
231#endif /* ASSEMBLER */
232
233#endif /* ! _PEXPERT_ARM_ARM64_H */
234