1/*
2 * Copyright (c) 2007-2017 Apple Inc. All rights reserved.
3 * Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved.
4 */
5#ifndef _PEXPERT_ARM_BOARD_CONFIG_H
6#define _PEXPERT_ARM_BOARD_CONFIG_H
7
8#include <mach/machine.h>
9
10#ifdef ARM64_BOARD_CONFIG_S5L8960X
11#define APPLE_ARM64_ARCH_FAMILY 1
12#define APPLECYCLONE
13#define ARM_ARCH_TIMER
14#include <pexpert/arm64/S5L8960X.h>
15#define __ARM_L2CACHE_SIZE_LOG__ 20
16#define ARM_BOARD_WFE_TIMEOUT_NS 1000
17#define ARM_BOARD_CLASS_S5L8960X
18#define KERNEL_INTEGRITY_WT 1
19#define PEXPERT_NO_3X_IMAGES 1
20#define CORE_NCTRS 8
21#endif /* ARM64_BOARD_CONFIG_S5L8960X */
22
23#ifdef ARM64_BOARD_CONFIG_T7000
24#define APPLE_ARM64_ARCH_FAMILY 1
25#define APPLETYPHOON
26#define ARM_ARCH_TIMER
27#include <pexpert/arm64/T7000.h>
28#define __ARM_L2CACHE_SIZE_LOG__ 20
29#define ARM_BOARD_WFE_TIMEOUT_NS 1000
30#define ARM_BOARD_CLASS_T7000
31#define KERNEL_INTEGRITY_WT 1
32#define CORE_NCTRS 8
33#endif /* ARM64_BOARD_CONFIG_T7000 */
34
35#ifdef ARM64_BOARD_CONFIG_T7001
36#define APPLE_ARM64_ARCH_FAMILY 1
37#define APPLETYPHOON
38#define ARM_ARCH_TIMER
39#include <pexpert/arm64/T7000.h>
40#define __ARM_L2CACHE_SIZE_LOG__ 21
41#define ARM_BOARD_WFE_TIMEOUT_NS 1000
42#define ARM_BOARD_CLASS_T7000
43#define KERNEL_INTEGRITY_WT 1
44#define CPU_COUNT 3
45#define CORE_NCTRS 8
46#endif /* ARM64_BOARD_CONFIG_T7001 */
47
48#ifdef ARM64_BOARD_CONFIG_S8000
49/*
50 * The L2 size for twister is in fact 3MB, not 4MB; we round up due
51 * to the code being architected for power of 2 cache sizes, and rely
52 * on the expected behavior that out of bounds operations will be
53 * ignored.
54 */
55#define APPLE_ARM64_ARCH_FAMILY 1
56#define APPLETWISTER
57#define ARM_ARCH_TIMER
58#include <pexpert/arm64/S8000.h>
59#define __ARM_L2CACHE_SIZE_LOG__ 22
60#define ARM_BOARD_WFE_TIMEOUT_NS 1000
61#define ARM_BOARD_CLASS_S8000
62#define KERNEL_INTEGRITY_WT 1
63#define CORE_NCTRS 8
64#endif /* ARM64_BOARD_CONFIG_S8000 */
65
66#ifdef ARM64_BOARD_CONFIG_S8001
67/*
68 * The L2 size for twister is in fact 3MB, not 4MB; we round up due
69 * to the code being architected for power of 2 cache sizes, and rely
70 * on the expect behavior that out of bounds operations will be
71 * ignored.
72 */
73#define APPLE_ARM64_ARCH_FAMILY 1
74#define APPLETWISTER
75#define ARM_ARCH_TIMER
76#include <pexpert/arm64/S8000.h>
77#define __ARM_L2CACHE_SIZE_LOG__ 22
78#define ARM_BOARD_WFE_TIMEOUT_NS 1000
79#define ARM_BOARD_CLASS_S8000
80#define KERNEL_INTEGRITY_WT 1
81#define CORE_NCTRS 8
82#endif /* ARM64_BOARD_CONFIG_S8001 */
83
84#ifdef ARM64_BOARD_CONFIG_T8010
85/*
86 * The L2 size for hurricane/zephyr is in fact 3MB, not 4MB; we round up due
87 * to the code being architected for power of 2 cache sizes, and rely
88 * on the expect behavior that out of bounds operations will be
89 * ignored.
90 */
91#define APPLE_ARM64_ARCH_FAMILY 1
92#define APPLEHURRICANE
93#define ARM_ARCH_TIMER
94#define KERNEL_INTEGRITY_KTRR
95#include <pexpert/arm64/T8010.h>
96#define __ARM_L2CACHE_SIZE_LOG__ 22
97#define ARM_BOARD_WFE_TIMEOUT_NS 1000
98#define ARM_BOARD_CLASS_T8010
99#define CORE_NCTRS 10
100#if DEVELOPMENT || DEBUG
101#define PMAP_CS 1
102#define PMAP_CS_ENABLE 0
103#endif
104#endif /* ARM64_BOARD_CONFIG_T8010 */
105
106#ifdef ARM64_BOARD_CONFIG_T8011
107#define APPLE_ARM64_ARCH_FAMILY 1
108#define APPLEHURRICANE
109#define ARM_ARCH_TIMER
110#define KERNEL_INTEGRITY_KTRR
111#include <pexpert/arm64/T8010.h>
112#define __ARM_L2CACHE_SIZE_LOG__ 23
113#define ARM_BOARD_WFE_TIMEOUT_NS 1000
114#define ARM_BOARD_CLASS_T8011
115#define CPU_COUNT 3
116#define CORE_NCTRS 10
117#if DEVELOPMENT || DEBUG
118#define PMAP_CS 1
119#define PMAP_CS_ENABLE 0
120#endif
121#endif /* ARM64_BOARD_CONFIG_T8011 */
122
123#ifdef ARM64_BOARD_CONFIG_T8015
124/*
125 * The LLC size for monsoon is 8MB, but the L2E exposed to mistral is
126 * only 1MB. We use the larger cache size here. The expectation is
127 * that this may cause flushes from mistral to be less efficient
128 * (cycles will be wasted on unnecessary way/set operations), but it
129 * will be technically correct... the best kind of correct.
130 *
131 * And is an explicit flush from L2E to LLC something we'll ever want
132 * to do?
133 */
134#define APPLE_ARM64_ARCH_FAMILY 1
135#define APPLEMONSOON
136#define ARM_ARCH_TIMER
137#define KERNEL_INTEGRITY_KTRR
138#include <pexpert/arm64/T8015.h>
139#define __ARM_L2CACHE_SIZE_LOG__ 23
140#define ARM_BOARD_WFE_TIMEOUT_NS 1000
141#define ARM_BOARD_CLASS_T8015
142#define CPU_COUNT 6
143#define BROKEN_FRIGGING_SLEEP 1 /* Spurious wake: See rdar://problem/29762505 */
144#define HAS_UNCORE_CTRS 1
145#define UNCORE_VERSION 1
146#define UNCORE_PER_CLUSTER 0
147#define UNCORE_NCTRS 8
148#define CORE_NCTRS 10
149#if DEVELOPMENT || DEBUG
150#define PMAP_CS 1
151#define PMAP_CS_ENABLE 0
152#endif
153#endif /* ARM64_BOARD_CONFIG_T8015 */
154
155
156
157
158
159
160#ifdef ARM64_BOARD_CONFIG_BCM2837
161#define BCM2837
162#define BCM2837_BRINGUP
163#define ARM_ARCH_TIMER
164#include <pexpert/arm64/BCM2837.h>
165#define __ARM_L2CACHE_SIZE_LOG__ 19
166#define ARM_BOARD_CLASS_BCM2837
167#define CPU_COUNT 4
168#endif /* ARM64_BOARD_CONFIG_BCM2837 */
169
170#endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */
171