1 | /* |
2 | * Copyright (c) 2007-2016 Apple Inc. All rights reserved. |
3 | * |
4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
5 | * |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License |
8 | * Version 2.0 (the 'License'). You may not use this file except in |
9 | * compliance with the License. The rights granted to you under the License |
10 | * may not be used to create, or enable the creation or redistribution of, |
11 | * unlawful or unlicensed copies of an Apple operating system, or to |
12 | * circumvent, violate, or enable the circumvention or violation of, any |
13 | * terms of an Apple operating system software license agreement. |
14 | * |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. |
17 | * |
18 | * The Original Code and all software distributed under the License are |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and |
24 | * limitations under the License. |
25 | * |
26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
27 | */ |
28 | /* |
29 | * @OSF_COPYRIGHT@ |
30 | */ |
31 | |
32 | /* |
33 | * ARM CPU identification |
34 | */ |
35 | |
36 | #ifndef _MACHINE_CPUID_H_ |
37 | #define _MACHINE_CPUID_H_ |
38 | |
39 | #include <stdint.h> |
40 | #include <mach/boolean.h> |
41 | #include <machine/machine_cpuid.h> |
42 | #include <machine/machine_routines.h> |
43 | |
44 | typedef struct { |
45 | uint32_t arm_rev : 4, /* 00:03 revision number */ |
46 | arm_part : 12,/* 04:15 primary part number */ |
47 | arm_arch : 4,/* 16:19 architecture */ |
48 | arm_variant : 4,/* 20:23 variant */ |
49 | arm_implementor : 8;/* 24:31 implementor (0x41) */ |
50 | } arm_cpuid_bits_t; |
51 | |
52 | typedef union { |
53 | arm_cpuid_bits_t arm_info; /* ARM9xx, ARM11xx, and later processors */ |
54 | uint32_t value; |
55 | } arm_cpu_info_t; |
56 | |
57 | /* Implementor codes */ |
58 | #define CPU_VID_ARM 0x41 // ARM Limited |
59 | #define CPU_VID_DEC 0x44 // Digital Equipment Corporation |
60 | #define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc. |
61 | #define CPU_VID_MARVELL 0x56 // Marvell Semiconductor Inc. |
62 | #define CPU_VID_INTEL 0x69 // Intel ARM parts. |
63 | #define CPU_VID_APPLE 0x61 // Apple Inc. |
64 | |
65 | |
66 | /* ARM Architecture Codes */ |
67 | |
68 | #define CPU_ARCH_ARMv4 0x1 /* ARMv4 */ |
69 | #define CPU_ARCH_ARMv4T 0x2 /* ARMv4 + Thumb */ |
70 | #define CPU_ARCH_ARMv5 0x3 /* ARMv5 */ |
71 | #define CPU_ARCH_ARMv5T 0x4 /* ARMv5 + Thumb */ |
72 | #define CPU_ARCH_ARMv5TE 0x5 /* ARMv5 + Thumb + Extensions(?) */ |
73 | #define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */ |
74 | #define CPU_ARCH_ARMv6 0x7 /* ARMv6 */ |
75 | #define CPU_ARCH_ARMv7 0x8 /* ARMv7 */ |
76 | #define CPU_ARCH_ARMv7f 0x9 /* ARMv7 for Cortex A9 */ |
77 | #define CPU_ARCH_ARMv7s 0xa /* ARMv7 for Swift */ |
78 | #define CPU_ARCH_ARMv7k 0xb /* ARMv7 for Cortex A7 */ |
79 | |
80 | #define CPU_ARCH_ARMv8 0xc /* Subtype for CPU_TYPE_ARM64 */ |
81 | |
82 | #define CPU_ARCH_ARMv8E 0xd /* ARMv8.3a + Apple Private ISA Subtype for CPU_TYPE_ARM64 */ |
83 | |
84 | /* special code indicating we need to look somewhere else for the architecture version */ |
85 | #define CPU_ARCH_EXTENDED 0xF |
86 | |
87 | /* ARM Part Numbers */ |
88 | /* |
89 | * XXX: ARM Todo |
90 | * Fill out these part numbers more completely |
91 | */ |
92 | |
93 | /* ARM9 (ARMv4T architecture) */ |
94 | #define CPU_PART_920T 0x920 |
95 | #define CPU_PART_926EJS 0x926 /* ARM926EJ-S */ |
96 | |
97 | /* ARM11 (ARMv6 architecture) */ |
98 | #define CPU_PART_1136JFS 0xB36 /* ARM1136JF-S or ARM1136J-S */ |
99 | #define CPU_PART_1176JZFS 0xB76 /* ARM1176JZF-S */ |
100 | |
101 | /* G1 (ARMv7 architecture) */ |
102 | #define CPU_PART_CORTEXA5 0xC05 |
103 | |
104 | /* M7 (ARMv7 architecture) */ |
105 | #define CPU_PART_CORTEXA7 0xC07 |
106 | |
107 | /* H2 H3 (ARMv7 architecture) */ |
108 | #define CPU_PART_CORTEXA8 0xC08 |
109 | |
110 | /* H4 (ARMv7 architecture) */ |
111 | #define CPU_PART_CORTEXA9 0xC09 |
112 | |
113 | /* H7 (ARMv8 architecture) */ |
114 | #define CPU_PART_TYPHOON 0x2 |
115 | |
116 | /* H7G (ARMv8 architecture) */ |
117 | #define CPU_PART_TYPHOON_CAPRI 0x3 |
118 | |
119 | /* H8 (ARMv8 architecture) */ |
120 | #define CPU_PART_TWISTER 0x4 |
121 | |
122 | /* H8G H8M (ARMv8 architecture) */ |
123 | #define CPU_PART_TWISTER_ELBA_MALTA 0x5 |
124 | |
125 | /* H9 (ARMv8 architecture) */ |
126 | #define CPU_PART_HURRICANE 0x6 |
127 | |
128 | /* H9G (ARMv8 architecture) */ |
129 | #define CPU_PART_HURRICANE_MYST 0x7 |
130 | |
131 | /* H10 p-Core (ARMv8 architecture) */ |
132 | #define CPU_PART_MONSOON 0x8 |
133 | |
134 | /* H10 e-Core (ARMv8 architecture) */ |
135 | #define CPU_PART_MISTRAL 0x9 |
136 | |
137 | /* H11 p-Core (ARMv8 architecture) */ |
138 | #define CPU_PART_VORTEX 0xB |
139 | |
140 | /* H11 e-Core (ARMv8 architecture) */ |
141 | #define CPU_PART_TEMPEST 0xC |
142 | |
143 | /* M9 e-Core (ARMv8 architecture) */ |
144 | #define CPU_PART_TEMPEST_M9 0xF |
145 | |
146 | /* H11G p-Core (ARMv8 architecture) */ |
147 | #define CPU_PART_VORTEX_ARUBA 0x10 |
148 | |
149 | /* H11G e-Core (ARMv8 architecture) */ |
150 | #define CPU_PART_TEMPEST_ARUBA 0x11 |
151 | |
152 | /* H12 p-Core (ARMv8 architecture) */ |
153 | #define CPU_PART_LIGHTNING 0x12 |
154 | |
155 | /* H12 e-Core (ARMv8 architecture) */ |
156 | #define CPU_PART_THUNDER 0x13 |
157 | |
158 | #ifndef RC_HIDE_XNU_FIRESTORM |
159 | /* |
160 | * Whilst this is a Thunder-based SoC, it |
161 | * hasn't been released and should remain |
162 | * hidden in 2020 seeds. |
163 | */ |
164 | /* M10 e-Core (ARMv8 architecture) */ |
165 | #define CPU_PART_THUNDER_M10 0x26 |
166 | #endif |
167 | |
168 | #ifndef RC_HIDE_XNU_FIRESTORM |
169 | |
170 | /* H13 e-Core */ |
171 | #define CPU_PART_ICESTORM 0x20 |
172 | |
173 | /* H13 p-Core */ |
174 | #define CPU_PART_FIRESTORM 0x21 |
175 | |
176 | /* H13G e-Core */ |
177 | #define CPU_PART_ICESTORM_TONGA 0x22 |
178 | |
179 | /* H13G p-Core */ |
180 | #define CPU_PART_FIRESTORM_TONGA 0x23 |
181 | |
182 | #endif /* !RC_HIDE_XNU_FIRESTORM */ |
183 | |
184 | /* H13J e-Core */ |
185 | #define CPU_PART_ICESTORM_JADE_CHOP 0x24 |
186 | #define CPU_PART_ICESTORM_JADE_DIE 0x28 |
187 | |
188 | /* H13J p-Core */ |
189 | #define CPU_PART_FIRESTORM_JADE_CHOP 0x25 |
190 | #define CPU_PART_FIRESTORM_JADE_DIE 0x29 |
191 | |
192 | |
193 | |
194 | |
195 | |
196 | |
197 | |
198 | |
199 | |
200 | /* Cache type identification */ |
201 | |
202 | /* Supported Cache Types */ |
203 | typedef enum { |
204 | CACHE_WRITE_THROUGH, |
205 | CACHE_WRITE_BACK, |
206 | CACHE_READ_ALLOCATION, |
207 | CACHE_WRITE_ALLOCATION, |
208 | CACHE_UNKNOWN |
209 | } cache_type_t; |
210 | |
211 | typedef struct { |
212 | boolean_t c_valid; /* has this cache info been populated? */ |
213 | boolean_t c_unified; /* unified I & D cache? */ |
214 | uint32_t c_isize; /* in Bytes (ARM caches can be 0.5 KB) */ |
215 | boolean_t c_i_ppage; /* protected page restriction for I cache |
216 | * (see B6-11 in ARM DDI 0100I document). */ |
217 | uint32_t c_dsize; /* in Bytes (ARM caches can be 0.5 KB) */ |
218 | boolean_t c_d_ppage; /* protected page restriction for I cache |
219 | * (see B6-11 in ARM DDI 0100I document). */ |
220 | cache_type_t c_type; /* WB or WT */ |
221 | uint32_t c_linesz; /* number of bytes */ |
222 | uint32_t c_assoc; /* n-way associativity */ |
223 | uint32_t c_l2size; /* L2 size, if present */ |
224 | uint32_t c_bulksize_op; /* bulk operation size limit. 0 if disabled */ |
225 | uint32_t c_inner_cache_size; /* inner dache size */ |
226 | } cache_info_t; |
227 | |
228 | typedef struct { |
229 | uint32_t |
230 | RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */ |
231 | SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */ |
232 | DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */ |
233 | TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */ |
234 | D:4, /* 19:16 - VFP hardware divide supported: 0x1 */ |
235 | SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */ |
236 | SV:4, /* 27:24 - VFP short vector supported: 0x1 */ |
237 | RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */ |
238 | } arm_mvfr0_t; |
239 | |
240 | typedef union { |
241 | arm_mvfr0_t bits; |
242 | uint32_t value; |
243 | } arm_mvfr0_info_t; |
244 | |
245 | typedef struct { |
246 | uint32_t |
247 | FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */ |
248 | DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */ |
249 | LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */ |
250 | I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */ |
251 | SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */ |
252 | HPFP:4, /* 23:20 - Half precision floating-point instructions supported */ |
253 | RSVP:8; /* 31:24 - Reserved */ |
254 | } arm_mvfr1_t; |
255 | |
256 | typedef union { |
257 | arm_mvfr1_t bits; |
258 | uint32_t value; |
259 | } arm_mvfr1_info_t; |
260 | |
261 | typedef struct { |
262 | uint32_t neon; |
263 | uint32_t neon_hpfp; |
264 | uint32_t neon_fp16; |
265 | } arm_mvfp_info_t; |
266 | |
267 | #ifdef __cplusplus |
268 | extern "C" { |
269 | #endif /* __cplusplus */ |
270 | |
271 | extern void do_cpuid(void); |
272 | extern arm_cpu_info_t *cpuid_info(void); |
273 | extern int cpuid_get_cpufamily(void); |
274 | extern int cpuid_get_cpusubfamily(void); |
275 | |
276 | extern void do_debugid(void); |
277 | extern arm_debug_info_t *arm_debug_info(void); |
278 | |
279 | extern void do_cacheid(void); |
280 | extern cache_info_t *cache_info(void); |
281 | extern cache_info_t *cache_info_type(cluster_type_t cluster_type); |
282 | |
283 | extern void do_mvfpid(void); |
284 | extern arm_mvfp_info_t *arm_mvfp_info(void); |
285 | |
286 | #ifdef __cplusplus |
287 | } |
288 | #endif /* __cplusplus */ |
289 | |
290 | #endif // _MACHINE_CPUID_H_ |
291 | |