1/*
2 * Copyright (c) 2012-2015 Apple Inc. All rights reserved.
3 */
4
5#ifndef _PEXPERT_ARM64_COMMON_H
6#define _PEXPERT_ARM64_COMMON_H
7
8/* This block of definitions is misplaced to shelter it from lines that will be
9 * removed in rdar://56937184. These definitions must be moved back after that
10 * change has been merged. */
11#ifdef APPLE_ARM64_ARCH_FAMILY
12#endif
13
14#ifdef ASSEMBLER
15#define __MSR_STR(x) x
16#else
17#define __MSR_STR1(x) #x
18#define __MSR_STR(x) __MSR_STR1(x)
19#endif
20
21#ifdef APPLE_ARM64_ARCH_FAMILY
22
23
24
25#if defined(APPLETYPHOON) || defined(APPLETWISTER)
26#define ARM64_REG_CYC_CFG_skipInit (1ULL<<30)
27#define ARM64_REG_CYC_CFG_deepSleep (1ULL<<24)
28#else /* defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER) */
29#define ARM64_REG_ACC_OVRD_enDeepSleep (1ULL << 34)
30#define ARM64_REG_ACC_OVRD_disPioOnWfiCpu (1ULL << 32)
31#define ARM64_REG_ACC_OVRD_dsblClkDtr (1ULL << 29)
32#define ARM64_REG_ACC_OVRD_cpmWakeUp_mask (3ULL << 27)
33#define ARM64_REG_ACC_OVRD_cpmWakeUp_force (3ULL << 27)
34#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_mask (3ULL << 25)
35#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deny (2ULL << 25)
36#define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deepsleep (3ULL << 25)
37#define ARM64_REG_ACC_OVRD_ok2TrDnLnk_mask (3ULL << 17)
38#define ARM64_REG_ACC_OVRD_ok2TrDnLnk_deepsleep (3ULL << 17)
39#define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_mask (3ULL << 15)
40#define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_deepsleep (2ULL << 15)
41#define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_mask (3ULL << 13)
42#define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_deepsleep (3ULL << 13)
43#endif /* defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER) */
44
45#define ARM64_REG_CYC_OVRD_irq_mask (3<<22)
46#define ARM64_REG_CYC_OVRD_irq_disable (2<<22)
47#define ARM64_REG_CYC_OVRD_fiq_mask (3<<20)
48#define ARM64_REG_CYC_OVRD_fiq_disable (2<<20)
49#define ARM64_REG_CYC_OVRD_ok2pwrdn_force_up (2<<24)
50#define ARM64_REG_CYC_OVRD_ok2pwrdn_force_down (3<<24)
51#define ARM64_REG_CYC_OVRD_disWfiRetn (1<<0)
52
53#if defined(APPLEMONSOON)
54#define ARM64_REG_CYC_OVRD_dsblSnoopTime_mask (3ULL << 30)
55#define ARM64_REG_CYC_OVRD_dsblSnoopPTime (1ULL << 31) /// Don't fetch the timebase from the P-block
56#endif /* APPLEMONSOON */
57
58#define ARM64_REG_LSU_ERR_STS_L1DTlbMultiHitEN (1ULL<<54)
59#define ARM64_REG_LSU_ERR_CTL_L1DTlbMultiHitEN (1ULL<<3)
60
61
62
63#if defined(HAS_IPI)
64#define ARM64_REG_IPI_RR_TYPE_IMMEDIATE (0 << 28)
65#define ARM64_REG_IPI_RR_TYPE_RETRACT (1 << 28)
66#define ARM64_REG_IPI_RR_TYPE_DEFERRED (2 << 28)
67#define ARM64_REG_IPI_RR_TYPE_NOWAKE (3 << 28)
68
69#define ARM64_IPISR_IPI_PENDING (1ull << 0)
70#endif /* defined(HAS_IPI) */
71
72
73
74#endif /* APPLE_ARM64_ARCH_FAMILY */
75
76
77#if defined(HAS_BP_RET)
78#define ARM64_REG_ACC_CFG_bdpSlpEn (1ULL << 2)
79#define ARM64_REG_ACC_CFG_btpSlpEn (1ULL << 3)
80#define ARM64_REG_ACC_CFG_bpSlp_mask 3
81#define ARM64_REG_ACC_CFG_bpSlp_shift 2
82#endif /* defined(HAS_BP_RET) */
83
84
85
86#define MPIDR_PNE_SHIFT 16 // pcore not ecore
87#define MPIDR_PNE (1 << MPIDR_PNE_SHIFT)
88
89
90#define CPU_PIO_CPU_STS_OFFSET (0x100ULL)
91#define CPU_PIO_CPU_STS_cpuRunSt_mask (0xff)
92
93/*
94 * CORE_THRTL_CFG2 non-sysreg tunable
95 */
96#define CORE_THRTL_CFG2_OFFSET (0x218)
97
98#define CORE_THRTL_CFG2_c1pptThrtlRate_shift (56)
99#define CORE_THRTL_CFG2_c1pptThrtlRate_mask (0xFFULL << CORE_THRTL_CFG2_c1pptThrtlRate_shift)
100
101
102
103
104#ifdef ASSEMBLER
105
106/*
107 * arg0: register in which to store result
108 * 0=>not a p-core, non-zero=>p-core
109 */
110.macro ARM64_IS_PCORE
111#if defined(APPLEMONSOON) || HAS_CLUSTER
112 mrs $0, MPIDR_EL1
113 and $0, $0, #(MPIDR_PNE)
114#endif /* defined(APPLEMONSOON) || HAS_CLUSTER */
115.endmacro
116
117/*
118 * reads a special purpose register, using a different msr for e- vs. p-cores
119 * arg0: register indicating the current core type, see ARM64_IS_PCORE
120 * arg1: register in which to store the result of the read
121 * arg2: SPR to use for e-core
122 * arg3: SPR to use for p-core or non-AMP architecture
123 */
124.macro ARM64_READ_EP_SPR
125#if defined(APPLEMONSOON) || HAS_CLUSTER
126 cbnz $0, 1f
127// e-core
128 mrs $1, $2
129 b 2f
130// p-core
1311:
132#endif /* defined(APPLEMONSOON) || HAS_CLUSTER */
133 mrs $1, $3
1342:
135.endmacro
136
137/*
138 * writes a special purpose register, using a different msr for e- vs. p-cores
139 * arg0: register indicating the current core type, see ARM64_IS_PCORE
140 * arg1: register containing the value to write
141 * arg2: SPR to use for e-core
142 * arg3: SPR to use for p-core or non-AMP architecture
143 */
144.macro ARM64_WRITE_EP_SPR
145#if defined(APPLEMONSOON) || HAS_CLUSTER
146 cbnz $0, 1f
147// e-core
148 msr $2, $1
149 b 2f
150// p-core
1511:
152#endif /* defined(APPLEMONSOON) || HAS_CLUSTER */
153 msr $3, $1
1542:
155.endmacro
156
157#endif /* ASSEMBLER */
158
159#endif /* ! _PEXPERT_ARM_ARM64_H */
160